Memory devices are present in all electronic systems for storing data. The base components which form them, the memory cells, are still the subject of intense research to improve their performance (retention, reliability, programming speed) especially by means of so-called innovative memory. The term “innovative” is understood to mean that they use storage mechanisms that until now have not been exploited in the field of electronics or else that they are novel in their architectures.
In the design of nonvolatile memory devices the following are sought: a high capacity, greatly reduced access times and a high data rate. The capacity represents the volume of information (generally expressed in bits) that the memory can store. The access time corresponds to the time interval between the read/write request and the availability of data. The data rate defines the volume of information exchanged per unit of time, expressed in bits per second. The “nonvolatility” characterizes the ability of a memory to retain the data when it is no longer powered.
Several types of memory exist. Random access memory, generally called RAM, especially including DRAM memory (dynamic random access memory), is of volatile type as it enables data to be stored only when it is powered. Read-only memory, called ROM, is nonvolatile and makes it possible to retain information which is contained therein even when it is no longer powered. Flash memory possesses the nonvolatility of read-only memory while being easily accessible when reading or writing. The name “flash” comes from the fact that the memory erasing operations are very rapid (about 10 s/byte).
Flash memory was designed so that an individual memory cell could be electrically programmed individually, and that a large number of individual cells, called a block, sector or page, could be electrically erased at the same time. Flash memory simultaneously combines the high density of EPROM memory (Erasable Programmable Read-Only Memory) and the system electrical erasing of EEPROM (Electrically Erasable Programmable Read-Only Memory).
There are two different flash memory technologies that are differentiated by the organization of their memory networks: the NOR and NAND architectures. NOR architecture provides an assembly of individual memory cells in parallel with selection lines as in a conventional EEPROM. NAND architecture provides an assembly, in series, of the same individual cells with the selection lines. The two NOR and NAND architectures both exploit the same principle of charge storage in the floating gate of a field-effect transistor.
The expression “floating gate” denotes an additional electrically isolated gate having a charge storage role. It is generally located between the channel and the control gate (FIG. 1). In MOS (Metal Oxide Semiconductor) technology, the floating gate is typically made of n-doped polycrystalline silicon (or polysilicon).
The operating principle of so-called floating gate semiconductor memory such as flash memory is to increase the threshold voltage Vth of certain transistors beyond the supply voltage in order to render them nonconductive during read cycles. The points corresponding to transistors with increased threshold voltages will therefore be in the “1” state (written or programmed state), the other in the “0” state (erased state).
The writing step corresponding to the increase in the threshold voltage is obtained by injection of electrons into the floating gate. The writing may be carried out according to two different mechanisms. The first consists of writing by Fowler-Nordheim tunneling. This is a question of applying a high positive voltage (between 10 and 20 V) to the control gate while keeping the drain and the source grounded. The electrons of the channel then tunnel through the tunnel dielectric and charge the floating gate. The second mechanism consists in writing by hot carrier injection. A high positive voltage is still applied to the gate, and also to the drain (drain voltage VD˜control gate voltage VCG/2), the source being kept grounded. The drain voltage then induces a strong electric field in the channel which allows the electrons to acquire a high enough energy to overcome the energy barrier that constitutes the tunnel dielectric and therefore charge the floating gate. Since writing by Fowler-Nordheim tunneling is quite slow (of the order of a millisecond), it is carried out by a block of cells. Since writing by hot carrier injection is itself faster, but consumes more energy, it allows selective access to a single memory point. The charge stored in this floating gate therefore induces a shift in the ID (VCG) characteristic (drain current ID as a function of the control gate voltage VCG) of the transistor, Reading is carried out by applying a voltage to the control gate between the two threshold voltages—Vth1 of the “erased” state and Vth2 of the “written” state (FIG. 2). The erasing operation consists in removing the electrons stored in the floating gate by applying a negative voltage to the control gate. The mechanism used for electrical erasure of floating gate structures is Fowler-Nordheim tunneling. This erasure may be carried out via the channel, via the source or else via both the source and the channel. The performance of nonvolatile memories, especially including flash memories, must meet certain functionality and reliability criteria. In particular, the programmed information must be retained for a period of at least ten years. Furthermore, the endurance of current flash memory must achieve 105 to 106 write/read cycles without variation between the two threshold voltages, Vth1 of the “erased” state and Vth2 of the “written” state.
Memory capacity has not ceased to increase despite the miniaturization of the individual cells of memory devices. However, several technological obstacles oppose the ever-increasing miniaturization of memory devices. Thus, the reduction in the dimensions of memory devices is accompanied by a reduction in the thicknesses of the dielectrics, in particular of the gate oxide. It is furthermore expected that by 2007, the thicknesses of tunnel oxide will be 8-9 nm for NOR gates and 6-7 nm for NAND gates (source: International Technology Roadmap for Semiconductor 2004 (ITRS 2004) [http://www.itrs.net/Common/2004Update/2004Update.htm].). However, to reduce the thickness of the tunnel oxide, in particular to below 8 nm, causes larger leakage currents. These leakage currents are induced either by direct tunneling, or by defects in the oxide that result from repeated writing and erasing operations (SILC for “Strain Induced Leakage Current”) The integrity of the programmed information is therefore affected thereby.
RAM memory is capable, thanks to its CMOS (complementary MOS) architecture, of operating at voltages of around 1 to 2 V. On the other hand, flash memory requires much higher usage voltages. In order to reduce the energy consumption, it would therefore be particularly advantageous to develop memory devices which would be capable of operating at voltages almost identical to those of CMOS transistors.
In order to meet the growing demand for miniaturization and improvement in the properties of memory devices (reduced consumption, high capacity with greatly reduced access time, high data rates, retention), novel architectures and novel materials are currently being studied.
Mention may especially be made of the adaptation of the FinFET architecture whose double-gate transistor has a flash functionality (S. Jacob et al., Proceedings of IEEE 1st International Conference on Memory Technology and Design, 153-156, 2005, May 21-24, Giens, France).
It has also been proposed to retain the flash architecture and to incorporate discrete trapping sites within the floating gate. The discrete trapping sites have the advantage of being electrically isolated from one another. Two main types of memory with discrete storage sites are currently known:
Nitride memory of SONOS (Silicon Oxide Nitride Oxide Silicon) type or of NROM (Nitride ROM) type, in which the electrons are trapped in defects located in a layer of silicon nitride (Si3N4) (B. Eitan et al., IEEE Electron Device Letters, 2000, 21:11:543-545). This type of memory advantageously has a high trapping site density (of the order of 1013/cm2). However, the injection of electrons into the nitride layer by the control gate during the erasing phase leads to a saturation of the erasing characteristics (M. Sadd et al, IEEE Non-volatile Semiconductor Memory Workshop 2003, p. 71).
Silicon nanocrystal memory has also been developed. The nanocrystals, whose size varies approximately from 5 to 10 nm, constitute discrete trapping sites. However, such memory is obtained by complex processes which limit the future miniaturization thereof.
The use of organic compounds having redox properties as discrete trapping sites in a floating gate of a flash memory seems to be a promising alternative to the use of conventional semiconductors. In order to be adapted to such a use, the organic compounds must imperatively fulfill the same requirements as those of the semiconductor materials, especially including being thermally stable in order to withstand the very high temperatures used during the manufacture of the memory cells or during their use.
Molecular memory of flash type that is already known uses floating gates comprising redox organic compounds which are oxidized electrostatically or electrochemically (US 2003/0111670 A1). The redox reactions of the organic compounds are controlled either by faradaic charge transfer, or by tunneling. This control makes it possible to modulate the capacity of the floating gate and therefore the threshold voltage of the transistor.
Li et al. (Appl. Phys. Lett., 2004, 84: 1949-1951) describe a memory cell of MOS transistor type comprising an In2O3 nanowire as the channel, a back control gate, and organic compounds as the floating gate. The compounds used are Fe2+ terpyridine complexes. The electrical properties of this memory cell correspond to an on/off ratio greater than 104, a functionality of three bits per cell (eight levels, due to three oxidation states) and a charge retention of 600 h. Other organic compounds such as fullerenes (Ganguly et al., Mat. Res. Symp. Proc., 2004, 789: 403-403) or metal complexes, especially including porphyrins (A, Yasseri et al., J. Amer. Chem. Soc., 2004, 126: 15603-15612), silicon-bridged metallocenes (Q. Li et al., Adv. Mat., 2004, 16: 133-137), or In2O3-bridged porphyrin (C. Li et al., J. Phys. Chem., 2004, 108: 9646-9649) have also been used in molecular memory. The latter have shown properties similar to that of Li et al.
Mixed self-assembled monolayers (SAMs) comprising zinc porphyrins and ferrocenes as charge storage molecules have been used in capacitor test cells (Q, Li et al., Advanced Materials, 2004, 16: 2, 133-137). These compounds have very different structures and their homogeneous distribution within the SAxs is difficult to control. Furthermore, the immobilization on a surface of a semiconductor or of the oxide by a SAM process is itself long, expensive and remains not very reproducible in terms of thickness and homogeneity of the layers. The SAMs obtained by a silanization step give rise to secondary polymerization reactions.
The term “self-assembled” denotes the spontaneous formation of complex hierarchical structures from simple elements. The self-assembling operation is based on the formation of SAM, LbL or Langmuir-Blodgett films. The forces involved in this operation are of supramolecular type, especially including van der Waals forces, dipolar forces and hydrogen bonds.
US 2003/111670 describes flash memory devices using, as charge storage molecules, various compounds with redox properties.
US 2005/162895 also describes memory devices, in particular of DRAM type, that use, as charge storage molecules, various compounds with redox properties.
Chaidogiannos et al. in Microelectronic Engineering, Vol. 73-74, (2004/06) pp. 746-751 and Glezos et al. in Applied Physics Letters, Vol. 83, No. 3, (2004/07/21) pp. 488-490 describe blends of polymers and of polyoxometallates as electronic charge carrier molecules.
Liu et al. describe, in Advanced Materials, Vol. 14, No. 3, Feb. 5, 2002 pp. 225-228, the use of polyoxometallates in an electrochromic device and study the optical stability effects of a multilayer assembly. They measure the color change due to changes in the redox state of particular polyoxometallates based on europium. The devices described do not make it possible to directly produce variations in the amounts of charge sufficient to obtain an electrical memory effect that can be used in DRAM and flash memory applications. It would be necessary, for example, for this purpose to couple them to a reading device so that they could perhaps constitute an electrical memory.
US-A-2003/0111670 describes a memory device of capacitive type comprising charge storage molecules, mainly of the porphyrin family, which are incorporated into a field-effect transistor between the channel and the control gate and which act as a floating gate. The molecules are grafted onto the channel and are encapsulated by an electrolyte, which acts as a control dielectric.
US-A-2005/0162895 describes memory devices and arrays of capacitive type comprising charge storage molecules mainly from the porphyrin family. The charge storage molecule device comprises an electrochemical cell forming a capacitor composed of two electrodes separated by an electrolyte and charge storage molecules encapsulated in an electrolyte coupled electronically to one of the two electrodes.
One of the main problems presented by the memory cells of the prior art is that they use organic compounds which are unstable, especially at high temperatures.
Specifically, it will be recalled that the organic compounds used in the memory cells of the prior art and which have redox properties are thermally unstable. For example, macrocyclic complexes, especially porphyrins or phthalocyanines, retain redox properties up to temperatures reaching 400° C. in an inert atmosphere, but begin to degrade from 200° C. The relative thermal stability of the compounds of the prior art confines their use to what are called back-gate transistors, whereas the fabricating processes of CMOS technologies favor front-gate transistors. This is because these processes involve the deposition of an oxide layer then of the gate onto the molecular layer at temperatures greater than 400° C.
The thermal instability which characterizes the organic compounds of the prior art poses a serious problem during the design of multibit storage memory cells. This is because the mixtures of organic compounds of different families having different degradation kinetics lead to modifications in the distribution of the compounds when very high temperatures are reached.
In particular, a memory device, especially of DRAM type, comprising a capacitor combined with a field-effect transistor, or of flash type and using at least one field-effect transistor, comprising organic compounds that are thermally stable and that have redox properties is not known.